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SM9403BM nippon precision circuits? nippon precision circuits inc. dvdram servo-ampli?r lsi overview the SM9403BM is a dvdrom and dvdram servo preprocessor lsi, designed for double-speed format dvdrom and dvdram drives. the SM9403BM is fabricated using a bicmos process, and incorporates an analog signal processing circuit that generates signals needed by the digital servo processor, a dpd signal processing circuit (dvdrom), and a capa (complementary allocated pit address) detection circuit (dvdram) all in a single chip. it operates from a single 5 v supply, and is available in 36-pin plastic ssop packages. features n dpd signal processor n tracking error signal output n focus error signal output n tracking error signal sample-and-hold n focus error signal sample-and-hold n capa detection function n track count pulse generator n off-track detection n 2v and 4v reference voltage generator n serial interface for setting internal parameters n sleep-mode function n single 5 v supply n 36-pin plastic ssop applications n double-speed dvdrom drives n double-speed dvdram drives ordering information pinout 36-pin ssop (top view) device package SM9403BM 36-pin ssop 1 nc 2 nc 3 fer 4 fhold 5 fsub 6 iset 7 dpdd 8 dpdc 9 dpdb 10 dpda 11 agnd 12 mmti 13 capan 14 capap 15 caplfc 16 tsub 17 thold 18 tre 19 vref4 20 vref2 21 troff 22 trp 23 caparea 24 capout 25 avcc 26 capin 27 capsel 28 capseek 29 dvcc 30 senb 31 sdata 32 sclk 33 dgnd 34 defect 35 dpdi 36 dpdg SM9403BM npc
SM9403BM nippon precision circuits? package dimensions (unit: mm) block diagram 2.44 to 2.64 0.85 15.20 to 15.40 7.40 to 7.60 0.29 to 0.39 0.80 0.10 to 0.30 0.51 to 1.01 10.11 to 10.51 0.63 0.10 7 0 to 8 0.23 to 0.32 7 0.51 0.20 45 r0.63 to 0.89 phase comparator lpf voltage reference s / h lpf serial interface s / h control dpdi dpdg iset vref2 vref4 fer fhold fsub tsub thold capap capan caplfc capin capout caparea capsel capseek trp troff tre senb sdata sclk dgnd dvcc agnd avcc vref2 dpda dpdb dpdc dpdd mono-multiviblator equalizer delay lpf analog signal processor s / h mmti swb track pulse generator swa defect * * *
SM9403BM nippon precision circuits? pin description number name i/o 1 1. i = input, ipd = input with b uilt-in pull-down resistor, i/o = input/output (n-channel open-drain when output), o = output function 1 nc o no connection 2 nc o no connection 3 fer o focus error signal output 4 fhold f ocus error hold capacitor connection 5 fsub i f ocus error signal input 6 iset i dpd signal equalizer, ref erence current set resistor connection 7 dpdd i dpd signal input d 8 dpdc i dpd signal input c 9 dpdb i dpd signal input b 10 dpda i dpd signal input a 11 ag n d analog circuit g round 12 mmti i mono-m ultivibr ator time-constant set resistor connection 13 c a pa n i id data signal differential inverting input 14 c a pa p i id data signal differential non-inverting input 15 caplfc slice-level detect capacitor connection 16 tsub i trac king error signal input 17 thold trac king error hold capacitor connection 18 tre o tracking error signal output 19 vref4 o 4v ref erence v oltage output 20 vref2 o 2v ref erence v oltage output 21 t ro f f o off-track detect signal output. low when off-track. 22 trp o track count pulse output. high-level pulse for land to outer tracking. 23 caparea o id interval detect signal output. id interval detected when high. 24 capout o outer offset id detect signal output. outer offset id interval detected when high. 25 av c c analog circuit pow er supply 26 capin o inner offset id detect signal output. inner offset id interval detected when high. 27 capsel ipd id interval signal input. id interval selected when high. 28 capseek ipd seek oper ation signal input. seek operation selected when high. 29 dv c c logic circuit pow er supply 30 senb i ser ial interf ace enable input. enabled when high. 31 s data i/o serial interf ace data input/ackno wledge output 32 sclk i ser ial interf ace clock input 33 dgnd logic circuit g round 34 defect ipd def ect position signal input. def ect position indicated when high. 35 dpdi i dpd signal hold delay set resistor connection 36 dpdg i dpd signal phase difference to voltage conver ter coef?ient set resistor connection
SM9403BM nippon precision circuits? specifications absolute maximum ratings gnd = 0 v recommended operating conditions gnd = 0 v recommended external components parameter symbol condition rating unit supply v oltage r ange v cc - 0.5 to 7.0 v input voltage r ange v in - 0.5 to v cc + 0.5 v oper ating temper ature r ange t opr 0 to 70 c stor age temper ature r ange t stg - 40 to 125 c pow er dissipation p d 250 m w soldering temperature t sld 260 c solder ing time t sld 10 s parameter symbol condition rating unit speci cations supply v oltage r ange v cc 4.75 to 5.25 v oper ating supply voltage r ange v cc 4.5 to 5.5 v oper ating temper ature r ange t opr 0 to 70 c pin no. pin name component t olerance 4 fhold 1000pf capacitor k (?0%) 6 iset 47k w resistor 1% 0.01? capacitor z (+80% to - 20%) 12 mmti 120k w resistor 1% 15 caplfc 0.01? capacitor z (+80% to - 20%) 17 thold 1000pf capacitor k (?0%) 19 vref4 0.1? capacitor z (+80% to - 20%) 20 vref2 0.1? capacitor z (+80% to - 20%) 35 dpdi 47k w resistor 1% 36 dpdg 33k w resistor 1%
SM9403BM nippon precision circuits? dc electrical characteristics v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c parameter symbol condition rating unit min typ max current consumption 1 1. 33k w resistor connected betw een dpdg and agnd 47k w resistor connected betw een dpdi and agnd 120k w resistor connected betw een mmti and agnd 47k w resistor connected betw een iset and agnd 1000pf capacitor connected betw een fhold and agnd 1000pf capacitor connected between thold and agnd 0.1? capacitor connected between vref4 and agnd 0.1? capacitor connected between vref2 and agnd 0.01? capacitor connected betw een caplfc and agnd 0.01? capacitor connected betw een iset and agnd capap, capan, dpda, dpdb, dpdc, dpdd, fsub, tsub connected to vref2 or other 2v supply. senb, sdata, sclk connected to gnd; all other pins (e xcluding supply and g round pins) open circuit. sleep mode 1: dpd system only in sleep condition. sleep mode 2: all blocks e xcept ref erence supply voltage gener ator in sleep condition. sleep mode 3: all blocks in sleep condition. i cc1 oper ating mode 28 34 ma i cc2 sleep mode 1 17 21 i cc3 sleep mode 2 2.0 2.6 i cc4 sleep mode 3 1.0 d i cc i cc1 - i cc2 9 capseek, capsel, defect, senb, sdata, sclk high-level input v oltage v ih 0.8v cc v capseek, capsel, defect, senb, sdata, sclk low-level input v oltage v il 0.2v cc v capseek, capsel, defect high-level input current i ih1 v in = v cc 50 100 200 a senb, sdata, sclk high-level input current i ih2 v in = v cc 3a capseek, capsel, defect, senb, sdata, sclk low-level input current i il v in = gnd - 3 a caparea, capin, capout, trp, troff high-level output v oltage v oh i oh = - 0.2ma v cc - 0.2 v caparea, capin, capout, trp, troff low -level output v oltage v ol1 i ol = 0.8ma 0.4 v s data low -level output v oltage v ol2 i ol = 7ma 1.0 v
SM9403BM nippon precision circuits? focus sample-and-hold, low-pass filter characteristics (fsub ? fer) v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c, fsub and fer signals in phase tracking sample-and-hold, low-pass filter characteristics (tsub ? tre) v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c, tsub and tre signals in phase parameter condition rating unit min typ max fsub input signal r ange vref2 reference - 1.25 0 +1.25 v fer output v oltage r ange vref2 reference - 1.25 0 +1.25 v fer output offset voltage vref2 reference, v in = v ref2 ?.0 m v fer output offset voltage temper ature drift vref2 reference 45 ?/ c fer output signal slew rate lpf off 1 v/? fer output load regulation i out = ?ma, v in = v ref2 ?0 mv fsub input impedance 100 k w fer output signal gain - 0.17 0 +0.17 db fer output signal bandwidth 1 1. c l = 20pf, r l = 500 w v in = 1.5vp-p, - 3db from dc lpf off (ffe = high) 500 khz lpf on (ffe = low) 115 160 230 fer output gain peaking 1 dc to - 3db frequency - 3 +0.5 db hold time fer output droop char acter istic v in = 200mvp-p, c fhold = 1000pf 0.025 %/? s/h acquisition time d v in = 200mv, target v alue ?10% 1 s fer output hold error with respect to the previous v alue 4 m v power-down state fer output impedance 1 m w parameter condition rating unit min typ max tsub input signal r ange vref2 reference - 1.25 0 +1.25 v tre output v oltage r ange vref2 reference - 1.25 0 +1.25 v tre output offset voltage vref2 reference, v in = v ref2 ?.0 m v tre output offset voltage temper ature drift vref2 reference 45 ?/ c tre output load regulation i out = ?ma, v in = v ref2 ?0 mv tsub input impedance 100 k w tre output signal gain - 0.17 0 +0.17 db tre output signal bandwidth 1 1. c l = 20pf, r l = 500 w v in = 1.5vp-p, - 3db from dc tfe = high 24 35 50 khz tfe = low 115 160 230 tre output gain peaking 1 dc to - 3db frequency - 3 +0.5 db hold time tre output droop char acter istic v in = 200mvp-p, c thold = 1000pf 0.025 %/? s/h acquisition time d v in = 200mv, target v alue ?0% 1 s tre output hold error with respect to the previous v alue 4 m v power-down state tre output impedance 1 m w
SM9403BM nippon precision circuits? dpd error signal detector characteristics (dpda/dpdb/dpdc/dpdd ? trp) v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c parameter 1 1. the tracking error signal tre is positive with respect to vref2 if the (dpda + dpdc) signal phase diff erence is leading. the detected phase diff erence is the diff erence betw een the point when one inter nal comparator output changes (from cma and cmb both high or both low) until the second output changes before the ?st changes again. the phase difference is conver ted to a v oltage and sampled for output. other signals are held constant in the output stage when a phase difference is detected. condition rating unit min typ max dpda/dpdb/dpdc/dpdd input v oltage range vref2 reference - 0.55 +1 v dpda/dpdb/dpdc/dpdd input impedance 1m w signal gain relative accuracy gain relative to dpda, dpdb, dpdc, dpdd inputs ?.17 db equalizer gain 1mhz setting dg2 =low 1.2 1.6 2.3 db dg2 = high 1.8 2.2 2.9 5mhz setting dg2 =low 5.5 6.1 6.6 dg2 = high 6.1 6.7 7.2 equalizer frequency response peak gain frequency (eqe = high) 3.75 5.0 6.25 mhz - 3db frequency (eqe = low) 11 22 33 equalizer frequency response relative accuracy f peak , (a + c) vs. (b + d) ?.5 % ac coupling time circuit - 3db frequency time constant 1 dg2 = low 56 84 109 khz time constant 2 dg2 = high 17 24 32 ac coupling time constant relative accuracy - 3db frequency, (a + c) vs. (b + d) 2 % delay control r ange see table 4. see table 4. ns phase diff erence detector minimum time dg1 = dg2 = low 2 ns phase diff erence detector maximum time dg1 = dg2 = high 1 ? phase diff erence detector minimum repeat time input pulse interval 120 ns phase difference to voltage conv ersion coef cient dg1 = dg2 = low see table 5. typ ?20% mv/ns phase difference to voltage conv ersion coef?ient change accuracy see table 8. 1 db phase difference output offset voltage vref2 reference ?.1 v phase difference output offset voltage temper ature drift vref2 reference ?70 v/ c defect signal response time 1 s dpd enable response time dpe ?g 2 ? abnormal waveform trp droop char acter istic v out = v ref2 ?200mv, vref2 reference 0.1 %/? trp output v oltage r ange vref2 reference - 1.25 0 +1.25 v trp output signal frequency response - 3db frequency 500 khz
SM9403BM nippon precision circuits? header position detector characteristics (capap/n ? caparea, capin, capout) v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c sample-and-hold control signal generator characteristics v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c tracking error signal switching characteristics (swa, swb) v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c parameter condition rating unit min typ max capap/n input v oltage r ange 1 3 v analog signal processor frequency response v in = v ref2 ?0.5v, - 3db from dc 13 mhz analog signal quantization slice level see table 9. typ ?15% v mono-m ultivibr ator time constant typ - 5% see table 10. typ + 45% s mono-m ultivibr ator time constant switching accuracy 5% mono-m ultivibr ator time-constant block interval accuracy ?.5 % capin, capout, cap area output r ise time and f all time c l = 20pf 15 ns parameter condition rating unit min typ max fer, tre output response time 1 1. fshcnt and tshcnt are the f ocus and tracking sample-and-hold inter nal control signals, respectively. mono-m ultivibr ator/capsel/capseek ? fshcnt/tshcnt 100 ns serial interf ace (hre, fhe, the, hae) ? fshcnt/tshcnt 2s parameter condition rating unit min typ max switching response time ser ial interf ace timing 1 s
SM9403BM nippon precision circuits? track count pulse generator characteristics (tsub ? trp, troff) v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c reference voltage generator characteristics (vref2, vref4) v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c parameter condition rating unit min typ max tsub input signal r ange vref2 reference - 1.25 +1.25 v tsub signal limiter voltage level vref2 reference ?.0 v tsub signal ampli?r gain f = 5khz 5.83 6.0 6.17 db quantization level offset set v alue typ - 15% see table 15 typ + 15% m v trp output compar ator hysteresis 1 1. trp has the same polar ity as tre (i.e. trp is high when tre > vref2). troff is high when the input signal is inside the window, and low when outside the window. typ - 10% see table 16 typ + 10% m v trp output compar ator hysteresis response time minimum h ysteresis, target v alue ?10% 600 ns trp output compar ator hysteresis switching response time minimum ? maximum h ysteresis v alue 2 s troff output compar ator window typ - 10% see table 17 typ + 10% m v troff output compar ator window switching response time minimum ? maximum window v alue 5 s parameter condition rating unit min typ max vref4 output v oltage v cc = 5v, t a = 25 c, i out = 0 3.84 4.0 4.16 v vref2 output v oltage 1.92 2.0 2.08 v vref4 output v oltage temper ature drift v cc = 5v, t a = 0 to 70 c, i out = 0 ?00 v/ c vref2 output v oltage temper ature drift ?00 v/ c vref4 output v oltage supply voltage dependency v cc = 5v ?5%, t a = 25 c, i out = 0 6mv vref2 output v oltage supply voltage dependency 3mv vref4 output v oltage load regulation v cc = 5v, t a = 25 c i out = 0 to 8ma - 20 mv vref2 output v oltage load regulation i out = 0 to ?ma 10 m v relative output voltage accuracy 1 1. dened as (vref2 - (vref4 ?2)). v cc = 5v, i out = 0 20 m v relative output v oltage temper ature drift v cc = 5v, t a = 0 to 70 c, i out = 0 10 v/ c relative output-voltage supply-voltage dependency v cc = 5v ?5%, t a = 25 c, i out = 0 1 m v vref4 pow er-down output impedance 13 k w vref2 pow er-down output impedance 1 m w
SM9403BM nippon precision circuits?0 serial interface characteristics (sclk, sdata, senb) v cc = 5v ?5%, gnd = 0v, t a = 0 to 70 c parameter symbol condition rating unit min typ max sclk pulse cycle t cysck 100 ns sclk high-level pulse width t whsck 40 ns sclk low-level pulse width t wlsck 40 ns senb setup time t ssen 20 ns senb hold time t hsen 40 ns sdata setup time t ssda 15 ns sdata hold time t hsda 15 ns ack setup time 1 1. ack is the acknowledge output (n-channel open-dr ain). low -level output when the data received is v alid. sdata load capacitance is 15pf. t sack 020ns ack hold time 1 t hack 50ns senb interval t insen 100 ns senb sclock sdata controller sdata port tssen twhsck twlclk tcysck tssda thsda tsack thack tinsen thsen bit 0 bit 1 bit 15 lsb msb ack high impedance
SM9403BM nippon precision circuits?1 functional description serial interface the SM9403BM uses a serial interface comprising 5 ports to control and set all functions. the address and bit con?uration of each port is shown in table 1 serial data is input on sdata with the lsb ?st, in sync with the falling edge of the sclk clock. after the 16th sclk falling edge and 16 bits of valid data has been input, the sdata n-channel open-drain output goes low as an acknowledge signal. if the number of sclk cycles which occur when senb (serial interface enable) is high is less than 16, the received data is ignored and the internal port is not updated. if the number of sclk cycles is greater than 16, the data is still considered value up to the 16th sclk falling edge, the data is latched into the internal port, and the acknowledge signal is output. the acknowledge signal is held until senb goes low again. focus sample-and-hold/low-pass filter (fsub ? fer) this stage, the signal which is generated from the header position detector signal samples and holds the focus error signal. the output then passes through a low-pass ?ter. this low-pass ?ter can be turned on or off using the serial interface control bit ffe. tracking sample-and-hold/low-pass filter (tsub ? tre) this stage, the signal which is generated from the header position detector signal samples and holds the tracking error signal. the output then passes through a low-pass ?ter. this low-pass ?ter cutoff frequency can be switched using the serial interface control bit tfe. table 1. port address and bit con?uration 1 bit n umber 1514131211109876543210 data address msb lsb dpe hae ffe tfe swb swa sl2 sl1 low low low high low of3 of2 of1 wd2 wd1 hs3 hs2 hs1 low low low high high the fhe hre mm2 mm1 ls3 ls2 ls1 low low high low low eqe cg3 cg2 cg1 dl4 dl3 dl2 dl1 low low high low high ts3 ts2 ts1 dg2 dg1 low low high high low 1. = don? care, = unassigned table 2. focus low-pass ?ter on/off control ffe low-pass lter 1 low on high off 1. default is on table 3. tracking low-pass ?ter cutoff frequency tfe low-pass lter 1 low f c = 160khz high f c = 35khz 1. default is 160khz
SM9403BM nippon precision circuits?2 dpd error signal detector (dpda/dpdb/dpdc/dpdd ? trp) this stage compares the dpd signals, passes the comparator output through a low-pass ?ter to obtain the dpd tracking error signal. the dpd signals are ?st added, (dpda + dpdc) and (dpdb + dpdd), then passed to an equalizer. a relative time delay is added for offset correction. the signals are then converted to a pulse waveform by comparators with hysteresis characteristics. the phase comparator then compares the phase of the pulse waveforms to obtain a time signal equiva- lent to the tracking error. the time signal is then con- verted to a voltage. the converted voltage is passed to the output stage, undergoes sampling timing compensation before being integrated to generate the tracking error signal output. the phase comparator incorporates a detector func- tion which prevents abnormal waveform signals get- ting to the output by holding the output constant. in addition, serial interface control bit dpe and input defect can be used to force the tracking error sig- nal to the reference voltage vref2. these controls can be used when powering up a system or to prevent output saturation from occurring during periods when the input signal is unstable. the relative time delay setting and time-to-voltage conversion coef?ient can be controlled using serial interface control bits. also, the equalizer used to compensate for the previous stage can be turned on or off using serial interface control.
SM9403BM nippon precision circuits?3 table 4. dpd delay time settings dg2 dg1 dl4 dl3 dl2 dl1 dpd delay (ns) 1 min typ max low low low low low low 0 0 0 low low low high - 2.2 - 3.0 - 3.3 low low high low - 4.2 - 5.6 - 6.4 low low high high - 6.0 - 8.0 - 9.5 low high low low - 7.5 - 11 - 13 low high low high - 10 - 14 - 16 low high high low - 12 - 17 - 20 low high high high - 14 - 20 - 24 high low low low +17 +24 +29 high low low high +14 +20 +23 high low high low +12 +17 +19 high low high high +10 +13 +15 high high low low +7.5 +11 +13 high high low high +5.6 +7.7 +9.0 high high high low +3.7 +5.5 +6.2 high high high high +2.0 +3.0 +3.4 low high low low low low 0 0 0 low low low high - 3.8 - 4.5 - 6.0 low low high low - 7.0 - 8.5 - 11 low low high high - 11 - 13 - 17 low high low low - 16 - 18 - 24 low high low high - 20 - 23 - 32 low high high low - 26 - 30 - 42 low high high high - 34 - 38 - 55 high low low low +44 +49 +74 high low low high +33 +37 +52 high low high low +25 +29 +38 high low high high +20 +22 +29 high high low low +15 +17 +22 high high low high +10 +12 +17 high high high low +7.0 +7.9 +11 high high high high +3.6 +4.3 +5.6 high low low low low low 0 0 0 low low low high - 7.0 - 8.5 - 13 low low high low - 15 - 17 - 24 low low high high - 22 - 27 - 36 low high low low - 32 - 37 - 50 low high low high - 43 - 48 - 65 low high high low - 55 - 62 - 83 low high high high - 70 - 78 - 108 high low low low +90 +100 +136 high low low high +70 +78 +102 high low high low +55 +61 +76 high low high high +42 +47 +60 high high low low +31 +36 +45 high high low high +22 +26 +34 high high high low +14 +17 +23 high high high high +7.2 +8.2 +12 high high low low low low 0 0 0 low low low high - 9.5 - 11 - 17 low low high low - 19 - 22 - 32 low low high high - 30 - 35 - 49 low high low low - 42 - 48 - 74 low high low high - 60 - 67 - 105 low high high low - 80 - 90 - 150 low high high high - 110 - 122 - 205 high low low low +124 +167 +210 high low low high +108 +120 +194 high low high low +80 +88 +130 high low high high +58 +65 +90 high high low low +42 +47 +64 high high low high +29 +33 +45 high high high low +18 +21 +31 high high high high +9.0 +10 +16 1. default is 0 ns (dl4 = dl3 = dl2 = dl1 = low) the dpd delay is positive when (a+c) leads (b+d). table 4. dpd delay time settings (continued) dg2 dg1 dl4 dl3 dl2 dl1 dpd delay (ns) 1 min typ max
SM9403BM nippon precision circuits?4 table 5. phase difference to voltage converter coef?ient cg3 cg2 cg1 coef cient (mv/ns) 1 low low low 5.38 low low high 7.58 low high low 10.7 low high high 15.2 high low low 21.4 high low high 30.3 high high low 42.7 high high high 60.6 1. default is 15.2 mv/ns table 6. equalizer control eqe equalizer 1 low off high on 1. default is off table 7. dpd output control dpe defect dpd output 1 low forced to vref2 high f orced to vref2 high low active 1. default is vref2 (dpe = low) table 8. dpd delay time coef?ient, phase difference to voltage converter coef?ient, ac coupling time constant dg2 dg1 phase to v oltage coef cient (relative to v alues in table 5) 1 dpd-ac coupling time constant cir cuit - 3db frequency selected media low low 1 100 khz 8-times cd, d vd-ram low high 1/2 4-times cd high low 1/4 25 khz 2-times cd high high 1/8 1-times cd 1. default is dg2 = dg1 = low
SM9403BM nippon precision circuits?5 header position detector (capap/n ? caparea, capin, capout) this stage converts a high-speed push-pull signal (capap/capan) to single-ended signals, passes the outputs through low-pass ?ters to form quan- tized logic levels which are used as reference signals. these reference signals are level shifted to form plus and minus signals for use by comparators. the amount of level shift can be controlled by serial interface control bits. after quantization logic conversion, retriggerable mono-multivibrators convert the pulse strings to con- tinuous signals. this creates inner shifted header capin and an outer shifted header capout output signals. in addition, the single-ended signal is also passed through a high-pass ?ter, which similarly converts to quantized logic signals. retriggerable mono-mul- tivibrators then convert the pulse strings to continu- ous signals to create a header area caparea signal. the mono-multivibrator time constants are con- trolled by serial interface control bits. table 9. slice level shift voltages ls3 ls2 ls1 level shift (mv) 1 1. default is ?5 mv low low low 25 low low high 50 low high low 75 low high high ?00 high low low ?25 high low high ?50 high high low ?00 high high high ?50 table 10. mono-multivibrator time constants mm2 mm1 capout/capin output (?) 1 1. default is 4 ? and (8 + a ), where a ? 6 ln(2v ls /v h ), v h = input sig- nal amplitude, v ls = slice level absolute v alue shown in table 9. caparea (?) 1 low low 4 8 + a low high 8 16 + a high low 12 24 + a high high 16 32 + a table 11. capout/capin/caparea logic capare a hae 1 1. default is low capout capin low low header signal output header signal output low high low low high low header signal output header signal output high high header signal output header signal output
SM9403BM nippon precision circuits?6 sample-and-hold control signal generator this stage takes the or-logic of the capin and capout signals, generated by the header position detector, the capsel and capseek input signals, and the serial interface control bit hre and uses them to create a sample-and-hold circuit control sig- nal shcnt. the shcnt is then used in conjunction with serial interface select bits fhe and the to form the focus sample-and-hold (fshcnt) and tracking sample- and-hold (tshcnt) signals. = don? care. = don? care. tracking error signal switching (swa, swb) this stage performs tracking error signal switching during dvdram write/read and dvdrom and cd playback. switching is controlled by serial interface control bits. table 12. sample-and-hold logic capin capout capsel capseek hre 1 shcnt high low high high high low high high low low low low high low low low high low low low high high high low high low 1. default is low table 13. sample-and-hold signal control logic fhe 1 1. default is low the 1 fshcnt 2 2. fshcnt is the f ocus sample-and-hold control signal, and tshcnt is the trac king sample-and-hold control signal. tshcnt 2 low low low low high shcnt high shcnt table 14. tracking error signal select swa swb tracking error signal select 1 1. default is s/h low low s/h high high dpd
SM9403BM nippon precision circuits?7 track count pulse generator (tsub ? trp, troff) this stage ?ters the tracking error signal through a 6th-order butterworth low-pass ?ter which effec- tively ?ters off header signal leakage effects. an off- set voltage is added and the signal passes through a comparator with hysteresis to generate a track count pulse signal output on trp. simultaneously, the win- dow comparator corresponding to the tracking error signal is output as the off-track signal on troff (low for off-track). the offset voltage, hysteresis level and window width are controlled by serial interface bits. sleep mode the SM9403BM features 3 sleep modes which can be used when the device is not operating to signi? cantly reduce current consumption. the sleep modes are controlled by serial interface bits. preset function when power is applied or in sleep modes 2 and 3, all serial interface ?gs are reset to their default values with the exception of the sleep mode ?gs sl2 and sl1 (see the section ?erial interface?. however, when writing data to sl2 and sl1 to cancel sleep mode, other ?gs in the same data word have prece- dence when writing to the port. table 15. offset voltage setting of3 of2 of1 offset voltage (mv) 1 1. default is 0 mv low low low 0 low low high - 200 low high low - 400 low high high - 600 high low low +800 high low high +600 high high low +400 high high high +200 table 16. trp comparator hysteresis hs3 hs2 hs1 hysteresis (mv) 1 low low low ?00 low low high ?00 low high low ?00 low high high ?00 high low low ?00 high low high 3 500 high high low 3 500 high high high 3 500 1. default is ?00 mv table 17. troff comparator window wd2 wd1 comparator window (mv) 1 low low ?25 low high ?50 high low ?75 high high ?75 1. default is ?25 mv table 18. sleep mode settings sl2 sl1 mode description 1 1. default is off (sl2 = sl1 = low) low low sleep mode off (normal oper ation) low high dpd in sleep condition high low all e xcept ref erence v oltage supply in sleep condition high high all blocks in sleep condition
SM9403BM nippon precision circuits?8 nippon precision circuits inc. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infr ingement. applications for any devices shown in this data sheet are for illustr ation only and nippon precision circuits inc. makes no claim or warranty that such applications will be suitable for the use speci?d without further testing o r modi?ation. the products described in this data sheet are not intended to use for the apparatus which in uence human lives due to the failure or malfunction of the products. customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. customers shall not e xport, directly or indirectly, any products without ?st obtaining required licenses and approv als from appropriate gover nment agencies. nippon precision circuits inc. 4-3, fukuzumi 2-chome koto-ku, tokyo 135-8430, j apan telephone: 03-3642-6661 facsimile: 03-3642-6698 nc9813ae 1999.09 nippon precision circuits inc.

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